On Wed, Aug 12, 2020 at 7:26 PM LIU Zhiwei wrote:
>
>
>
> On 2020/8/13 3:13, Alistair Francis wrote:
> > This series updates the experimental QEMU RISC-V Hypervisor spec to the
> > v0.6.1 draft implementation.
> >
> > THis includes support for the new 2-stage lookup instructions and the new
> > CS
On 2020/8/13 3:13, Alistair Francis wrote:
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
f
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
fault.
This was tested by running 32-bit and 64-