On Tue, 7 Feb 2023 10:50:56 +0800
"Wang, Lei" wrote:
> On 2/2/2023 7:05 PM, Igor Mammedov wrote:
> > On Fri, 6 Jan 2023 00:38:20 -0800
> > Lei Wang wrote:
> >
> >> This series aims to add a new CPU model SapphireRapids, and tries to
> >> address the problem stated in
> >> https://lore.kernel
On Thu, 2023-02-02 at 12:05 +0100, Igor Mammedov wrote:
> MultiBitFeatureInfo looks like an interesting
> idea
Yeah, we can feel how much effort Lei spent on this.
> but among fixing whatever issues this has atm,
> you'd probably need to introduce a new qdev_bitfield property
> infrastructure s
On 2/2/2023 7:05 PM, Igor Mammedov wrote:
On Fri, 6 Jan 2023 00:38:20 -0800
Lei Wang wrote:
This series aims to add a new CPU model SapphireRapids, and tries to
address the problem stated in
https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b2
On 2/2/2023 7:05 PM, Igor Mammedov wrote:
> On Fri, 6 Jan 2023 00:38:20 -0800
> Lei Wang wrote:
>
>> This series aims to add a new CPU model SapphireRapids, and tries to
>> address the problem stated in
>> https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65
On Fri, 6 Jan 2023 00:38:20 -0800
Lei Wang wrote:
> This series aims to add a new CPU model SapphireRapids, and tries to
> address the problem stated in
> https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb30,
> so that named CPU mode
This series aims to add a new CPU model SapphireRapids, and tries to
address the problem stated in
https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb30,
so that named CPU model can define its own AMX values, and QEMU won't
pass the wron
