On Wed, May 27, 2020 at 10:51 PM Thomas Huth wrote:
>
> On 27/05/2020 19.35, Alistair Francis wrote:
> > On Wed, May 27, 2020 at 12:17 AM Thomas Huth wrote:
> >>
> >> On 27/05/2020 00.47, Alistair Francis wrote:
> >>>
> >>> include/hw/riscv/spike.h | 6 +-
> >>> target/ris
On 27/05/2020 19.35, Alistair Francis wrote:
> On Wed, May 27, 2020 at 12:17 AM Thomas Huth wrote:
>>
>> On 27/05/2020 00.47, Alistair Francis wrote:
>>>
>>> include/hw/riscv/spike.h | 6 +-
>>> target/riscv/cpu.h| 8 -
>>> hw/riscv/spike.c
On Wed, May 27, 2020 at 12:17 AM Thomas Huth wrote:
>
> On 27/05/2020 00.47, Alistair Francis wrote:
> >
> > include/hw/riscv/spike.h | 6 +-
> > target/riscv/cpu.h| 8 -
> > hw/riscv/spike.c | 217 -
On 27/05/2020 00.47, Alistair Francis wrote:
>
> include/hw/riscv/spike.h | 6 +-
> target/riscv/cpu.h| 8 -
> hw/riscv/spike.c | 217 --
> target/riscv/cpu.c| 30 ---
>
v3:
- Don't use SiFive CPUs for Spike machine
v2:
- Remove the CPUs and ISA seperatley
Alistair Francis (3):
hw/riscv: spike: Remove deprecated ISA specific machines
target/riscv: Remove the deprecated CPUs
target/riscv: Drop support for ISA spec version 1.09.1
include/hw/riscv/spike.
