Re: [PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP

2022-03-17 Thread Alistair Francis
On Thu, Mar 17, 2022 at 4:18 PM Alistair Francis wrote: > > From: Alistair Francis > > The RISC-V specification states that: > "Supervisor-level external interrupts are made pending based on the > logical-OR of the software-writable SEIP bit and the signal from the > external interrupt cont

[PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP

2022-03-16 Thread Alistair Francis
From: Alistair Francis The RISC-V specification states that: "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller." We currently only allow either the interrupt controller or s