[PATCH v3 0/1] target/riscv: Add Zihintpause support

This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode. Added trans_pause for TCG to mainly to break reservation and exit the TB. The change can also be found in: https://github.com/dlu42/qemu/tree/zihintpause_support_v

[PATCH v3 0/1] target/riscv: Add Zihintpause support

This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode. Added trans_pause for TCG to mainly to break reservation and exit the TB. The change can also be found in: https://github.com/dlu42/qemu/tree/zihintpause_support_v