On Fri, 2021-03-26 at 07:11 -0600, Richard Henderson wrote:
> On 3/25/21 7:47 PM, Robert Hoo wrote:
> > On Thu, 2021-03-25 at 06:39 -0600, Richard Henderson wrote:
> > > On 3/24/21 9:15 PM, Robert Hoo wrote:
> > > > > > +} else if (env->xcr0 & XFEATURE_AVX) {
> > > > >
> > > > > This is no
On 3/25/21 7:47 PM, Robert Hoo wrote:
On Thu, 2021-03-25 at 06:39 -0600, Richard Henderson wrote:
On 3/24/21 9:15 PM, Robert Hoo wrote:
+} else if (env->xcr0 & XFEATURE_AVX) {
This is normally a 2-bit test.
I beg your pardon. What 2 bits?
I forget the names, but isn't the usual te
On Thu, 2021-03-25 at 06:39 -0600, Richard Henderson wrote:
> On 3/24/21 9:15 PM, Robert Hoo wrote:
> > > > +} else if (env->xcr0 & XFEATURE_AVX) {
> > >
> > > This is normally a 2-bit test.
> >
> > I beg your pardon. What 2 bits?
>
> I forget the names, but isn't the usual test xcr0 & 6
On 3/24/21 9:15 PM, Robert Hoo wrote:
+} else if (env->xcr0 & XFEATURE_AVX) {
This is normally a 2-bit test.
I beg your pardon. What 2 bits?
I forget the names, but isn't the usual test xcr0 & 6 == 6?
BTW, checkpatch didn't warn me on this. It escaped.:)
Heh.
r~
On Wed, 2021-03-24 at 07:44 -0600, Richard Henderson wrote:
> On 3/24/21 2:00 AM, Robert Hoo wrote:
> > +if ((env->xcr0 & XFEATURE_AVX512) == XFEATURE_AVX512) {
> > +/* XSAVE enabled AVX512 */
> > +nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
> > +for (i =
On 3/24/21 2:00 AM, Robert Hoo wrote:
+if ((env->xcr0 & XFEATURE_AVX512) == XFEATURE_AVX512) {
+/* XSAVE enabled AVX512 */
+nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
+for (i = 0; i < nb; i++) {
+qemu_fprintf(f, "ZMM%02d=0x%016lx %016lx
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
YMM/ZMM
