Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Tue, May 24, 2022 at 3:08 AM Alistair Francis wrote: > > On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote: > > > > We should write transformed instruction encoding of the trapped > > instruction in [m|h]tinst CSR at time of taking trap as defined > > by the RISC-V privileged specification v1.

Re: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote: > > We should write transformed instruction encoding of the trapped > instruction in [m|h]tinst CSR at time of taking trap as defined > by the RISC-V privileged specification v1.12. > > Signed-off-by: Anup Patel > --- > target/riscv/cpu_helper.c

[PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 168 +- target/riscv/instmap