Re: [PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

On Sat, May 27, 2023 at 2:24 AM Rajnesh Kanwal wrote: > > This is to allow virtual interrupts to be inserted into S and VS > modes. Given virtual interrupts will be maintained in separate > mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the > path and interrupts need to be triggered

[PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip.

This is to allow virtual interrupts to be inserted into S and VS modes. Given virtual interrupts will be maintained in separate mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the path and interrupts need to be triggered for these cases from rmw_hvip64 and rmw_mvip64 functions. Signe