On 2023/8/7 14:55, gaosong wrote:
Hi, Jiajie
在 2023/8/7 下午1:17, Jiajie Chen 写道:
On 2023/8/7 11:18, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 9 +
Hi, Jiajie
在 2023/8/7 下午1:17, Jiajie Chen 写道:
On 2023/8/7 11:18, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 9 +
target/loongarch/tlb_helper.c | 17 ++
On 2023/8/7 11:18, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertion
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/loo
