Re: [PATCH v2 3/9] target/riscv: Add MIPS P8700 CPU

2025-06-18 Thread Djordje Todorovic
On 10. 6. 25. 09:38, Philippe Mathieu-Daudé wrote: > CAUTION: This email originated from outside of the organization. Do > not click links or open attachments unless you recognize the sender > and know the content is safe. > > > Hi, > > On 2/6/25 15:12, Djordje Todorovic wrote: >> Introduce MIPS

Re: [PATCH v2 3/9] target/riscv: Add MIPS P8700 CPU

2025-06-10 Thread Philippe Mathieu-Daudé
Hi, On 2/6/25 15:12, Djordje Todorovic wrote: Introduce MIPS P8700 CPU and set reset vector to 0x1fc0. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 16 2 files changed, 17 insertions(+) diff

[PATCH v2 3/9] target/riscv: Add MIPS P8700 CPU

2025-06-02 Thread Djordje Todorovic
Introduce MIPS P8700 CPU and set reset vector to 0x1fc0. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 16 2 files changed, 17 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qo