On 10/31/20 6:25 PM, Joelle van Dyne wrote:
> Unfortunately this crashes on iOS/Apple Silicon macOS.
>
> (lldb) bt
> * thread #19, stop reason = EXC_BAD_INSTRUCTION (code=1, subcode=0xd53b002a)
> * frame #0: 0x0001169501e0
> libqemu-x86_64-softmmu.utm.dylib`tcg_prologue_init + 760
> ...
> (l
On 10/31/20 6:25 PM, Joelle van Dyne wrote:
> Another thing, for x86 (and maybe other archs), the icache is cache
> coherent but does it apply if we are aliasing the memory address? I
> think in that case, it's like we're doing a DMA right and still need
> to do flushing+invalidating?
No, it is no
Unfortunately this crashes on iOS/Apple Silicon macOS.
(lldb) bt
* thread #19, stop reason = EXC_BAD_INSTRUCTION (code=1, subcode=0xd53b002a)
* frame #0: 0x0001169501e0
libqemu-x86_64-softmmu.utm.dylib`tcg_prologue_init + 760
...
(lldb) x/i 0x0001169501e0
-> 0x1169501e0: 0xd53b002a mr
Copy the single pointer implementation from libgcc and modify it to
support the double pointer interface we require. This halves the
number of cache operations required when split-rwx is enabled.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 11 +---
tcg/aarch64/tcg-ta
