On 9/20/19 3:15 AM, Alex Bennée wrote:
> I can't figure out what is meant to be going on with CONVERT_BITS. It
> seems to be implying there is a direct relationship between status flags
> and the exception disable bits. But that is confusing because integer
> overflow (IOV) and float overflow (OVF)
Alex Bennée writes:
> Richard Henderson writes:
>
>> On 9/19/19 10:10 AM, Alex Bennée wrote:
>>> This is broadly similar to the existing fcvt test for ARM but using
>>> the generic float testing framework. We should be able to pare down
>>> the ARM fcvt test case to purely half-precision with
Richard Henderson writes:
> On 9/19/19 10:10 AM, Alex Bennée wrote:
>> This is broadly similar to the existing fcvt test for ARM but using
>> the generic float testing framework. We should be able to pare down
>> the ARM fcvt test case to purely half-precision with or without the
>> Alt HP prov
On 9/19/19 10:10 AM, Alex Bennée wrote:
> This is broadly similar to the existing fcvt test for ARM but using
> the generic float testing framework. We should be able to pare down
> the ARM fcvt test case to purely half-precision with or without the
> Alt HP provision.
>
> Signed-off-by: Alex Benn
This is broadly similar to the existing fcvt test for ARM but using
the generic float testing framework. We should be able to pare down
the ARM fcvt test case to purely half-precision with or without the
Alt HP provision.
Signed-off-by: Alex Bennée
---
tests/tcg/aarch64/float_convs.ref | 748 +
