On 12/30/22 12:35, Philippe Mathieu-Daudé wrote:
This SoC uses a Cortex-M4F. QEMU only implements a M4,
which is good enough. Add a TODO note in case the M4F
is added.
How complex would it be to add the FPU version of the M4 ? I suppose we have
all the instructions already implemented ?
Sign
This SoC uses a Cortex-M4F. QEMU only implements a M4,
which is good enough. Add a TODO note in case the M4F
is added.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Delevoryas
---
hw/arm/aspeed_ast10x0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspee
