Re: [PATCH v2 1/6] target/riscv: zfh: half-precision load and store

2021-10-15 Thread Richard Henderson
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote: +#define REQUIRE_ZFH(ctx) do { \ +if (!ctx->ext_zfh)\ +return false; \ +} while (0) Missing braces for if. Otherwise, Reviewed-by: Richard Henderson r~

[PATCH v2 1/6] target/riscv: zfh: half-precision load and store

2021-10-15 Thread frank . chang
From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 1 + target/riscv/insn32.decode| 4 ++ target/riscv/insn_trans/trans_rvzfh.c.i