On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
+/* Composite status for PMC[1-5] enabled and counting insns or cycles. */
+uint8_t pmc_ins_cnt;
+uint8_t pmc_cyc_cnt;
I should have updated the comment to 1-6 when I added cyc_cnt.
+sel = extract64(mmcr1, MMCR1_PMC4EVT_EX
From: Richard Henderson
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson
[danielhb: fixed PMC4 cyc_cnt shift and insn run latch code]
Signed-off-by: Daniel H
