On 8/2/24 03:05, Deepak Gupta wrote:
On Thu, Aug 1, 2024 at 2:12 AM Richard Henderson
wrote:
On 8/1/24 16:59, Deepak Gupta wrote:
hmm... you've suggested below to use `aarch64_tr_translate_insn` and
check if it's the first instruction.
and put the check there.
In that case I won't need FCFI_L
On Thu, Aug 1, 2024 at 2:12 AM Richard Henderson
wrote:
>
> On 8/1/24 16:59, Deepak Gupta wrote:
> > hmm... you've suggested below to use `aarch64_tr_translate_insn` and
> > check if it's the first instruction.
> > and put the check there.
> > In that case I won't need FCFI_LP_EXPECTED TB flag.
>
On 8/1/24 16:59, Deepak Gupta wrote:
hmm... you've suggested below to use `aarch64_tr_translate_insn` and
check if it's the first instruction.
and put the check there.
In that case I won't need FCFI_LP_EXPECTED TB flag.
Then I would rather use it as FCFI_ENABLED TB flag.
You will need both bits
On Mon, Jul 29, 2024 at 7:34 PM Richard Henderson
wrote:
>
> On 7/30/24 03:53, Deepak Gupta wrote:
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index acba90f170..c746d7df08 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -20,6 +20,7 @
On 7/30/24 03:53, Deepak Gupta wrote:
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index acba90f170..c746d7df08 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -20,6 +20,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "tcg/tcg-op.h"
+#include
zicfilp protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpad`. If
target of an indirect call or jmp is not `lpad` then cpu/hart must raise
a sw check exception with tval = 2.
This patch implements the mechanism using TCG. Ta