Re: [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support

On 8/30/24 16:15, LIU Zhiwei wrote: From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Wid

[PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support

From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multi