On 10/20/21 9:13 AM, Alex Bennée wrote:
Richard Henderson writes:
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC
Richard Henderson writes:
> Currently, we have support for optimizing redundant zero extensions,
> which I think was done with x86 and aarch64 in mind, which zero-extend
> all 32-bit operations into the 64-bit register.
>
> But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
>
Ping.
On 10/7/21 12:54 PM, Richard Henderson wrote:
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC-V do sign-extens
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
The last 5 patches address this.
But bef
