Re: [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support

2021-01-24 Thread Philippe Mathieu-Daudé
Hi Bin, On 1/23/21 11:39 AM, Bin Meng wrote: > From: Bin Meng > > This adds the missing SPI support to the `sifive_u` machine in the QEMU > mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed > board can boot on QEMU `sifive_u` out of the box. This allows users to > devel

[PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support

2021-01-23 Thread Bin Meng
From: Bin Meng This adds the missing SPI support to the `sifive_u` machine in the QEMU mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU `sifive_u` out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real w