Re: [PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU

2025-06-18 Thread Djordje Todorovic
On 10. 6. 25. 13:42, Alistair Francis wrote: > [You don't often get email from alistai...@gmail.com. Learn why this is > important at https://aka.ms/LearnAboutSenderIdentification ] > > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unle

Re: [PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU

2025-06-10 Thread Alistair Francis
On Mon, Jun 2, 2025 at 11:14 PM Djordje Todorovic wrote: > > Several things implemented in v2: > - Addressing review comments > - Simplify `target/riscv/xmips.decode` > - Rebase on top of latest master > - Fix code format > > Djordje Todorovic (9): > hw/intc: Allow gaps in hartids for

[PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU

2025-06-02 Thread Djordje Todorovic
Several things implemented in v2: - Addressing review comments - Simplify `target/riscv/xmips.decode` - Rebase on top of latest master - Fix code format Djordje Todorovic (9): hw/intc: Allow gaps in hartids for aclint and aplic target/riscv: Add cpu_set_exception_base target/riscv: