Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01

2023-10-11 Thread Mayuresh Chitale
On Mon, Oct 9, 2023 at 6:56 AM Alistair Francis wrote: > > On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale > wrote: > > > > As per the Priv spec: "The R, W, and X fields form a collective WARL > > field for which the combinations with R=0 and W=1 are reserved." > > However currently such writes

Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01

2023-10-08 Thread Alistair Francis
On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale wrote: > > As per the Priv spec: "The R, W, and X fields form a collective WARL > field for which the combinations with R=0 and W=1 are reserved." > However currently such writes are not ignored as ought to be. The > combinations with RW=01 are allo

Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01

2023-10-08 Thread Alistair Francis
On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale wrote: > > As per the Priv spec: "The R, W, and X fields form a collective WARL > field for which the combinations with R=0 and W=1 are reserved." > However currently such writes are not ignored as ought to be. The > combinations with RW=01 are allo

[PATCH v2] target/riscv: pmp: Ignore writes when RW=01

2023-09-25 Thread Mayuresh Chitale
As per the Priv spec: "The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved." However currently such writes are not ignored as ought to be. The combinations with RW=01 are allowed only when the Smepmp extension is enabled and mseccfg.MML is se