Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-11 Thread Alistair Francis
On Sun, Jul 10, 2022 at 9:05 PM Frédéric Pétrot wrote: > > For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c > it stays 0 and is a hint instruction that does not change processor state. > For rv128c right shifts, the 6-bit shamt is in addition sign extended to > 7 bits. > > S

Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-11 Thread Richard Henderson
On 7/12/22 01:24, Frédéric Pétrot wrote:   Agreed, on the non compressed insns, but the compressed ones have a 6-bit   shamt only as visible on page 18.6 page 125. The explanation for rv128 shifts   is further detailed in the emphasized paragraph on top of page 120. I see. I should have rea

Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-11 Thread Frédéric Pétrot
Hi Richard, Le 11/07/2022 à 06:44, Richard Henderson a écrit : On Sun, 10 July 2022, 16:36 Frédéric Pétrot, > wrote: For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not

Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-11 Thread Richard Henderson
On Sun, 10 July 2022, 16:36 Frédéric Pétrot, < frederic.pet...@univ-grenoble-alpes.fr> wrote: > For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c > it stays 0 and is a hint instruction that does not change processor state. > For rv128c right shifts, the 6-bit shamt is in addi

Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-10 Thread Weiwei Li
在 2022/7/10 下午7:04, Frédéric Pétrot 写道: For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Frédéric Pé

[PATCH v2] target/riscv: fix shifts shamt value for rv128c

2022-07-10 Thread Frédéric Pétrot
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 +