Re: [PATCH v2] target/riscv: Add RVV registers to log

On Fri, Mar 10, 2023 at 12:01 AM Ivan Klokov wrote: > > Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular regs. > > Signed-off-by: Ivan Klokov > --- > v2: >- fix option name >- fix byte ordering > --- > accel/tcg/cpu-exec.c | 3 +++ > include/hw/core/cpu.h | 2 ++

[PATCH v2] target/riscv: Add RVV registers to log

Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular regs. Signed-off-by: Ivan Klokov --- v2: - fix option name - fix byte ordering --- accel/tcg/cpu-exec.c | 3 +++ include/hw/core/cpu.h | 2 ++ include/qemu/log.h| 1 + target/riscv/cpu.c| 59 +++