Re: [PATCH v2] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32

2021-07-20 Thread David Gibson
On Tue, Jul 20, 2021 at 10:55:07AM -0300, matheus.fe...@eldorado.org.br wrote: > From: Matheus Ferst > > In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what > The Programming Environments Manual say: > > "For 32-bit implementations, the L field must be cleared, otherwise > th

Re: [PATCH v2] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32

2021-07-20 Thread Richard Henderson
On 7/20/21 3:55 AM, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what The Programming Environments Manual say: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Th

[PATCH v2] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32

2021-07-20 Thread matheus . ferst
From: Matheus Ferst In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what The Programming Environments Manual say: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." The stricter behavior, however, broke AROS boot on sam460ex,