Re: [PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

On Mon, Jan 6, 2025 at 12:15 PM Alistair Francis wrote: > On Tue, Dec 31, 2024 at 1:28 PM wrote: > > > > From: Tommy Wu > > > > This adds the properties for ISA extension Smrnmi. > > > > Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set > > mnstatus.NMIE to 1 before enabling a

Re: [PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

On Tue, Dec 31, 2024 at 1:28 PM wrote: > > From: Tommy Wu > > This adds the properties for ISA extension Smrnmi. > > Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all > interrupts will be disabled. Since our cur

[PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disabl