Re: [PATCH v11 12/14] target/riscv: rvk: add CSR support for Zkr

On Tue, Apr 19, 2022 at 12:06 PM Weiwei Li wrote: > > - add SEED CSR which must be accessed with a read-write instruction: >A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI > with uimm=0 will raise an illegal instruction exception. > - add USEED, SSEED fields for MSEC

[PATCH v11 12/14] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye