On Sat, Jan 06, 2024 at 11:33:29PM +0700, Bui Quang Minh wrote:
> On 12/28/23 22:44, Bui Quang Minh wrote:
> > On 12/26/23 16:21, Michael S. Tsirkin wrote:
> > > On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
> > > > Hi everyone,
> > > >
> > > > This series implements x2APIC mode
On 12/28/23 22:44, Bui Quang Minh wrote:
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. In
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to su
On Wed, Dec 27, 2023 at 06:03:46PM +0700, Bui Quang Minh wrote:
> On 12/26/23 16:21, Michael S. Tsirkin wrote:
> > On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
> > > Hi everyone,
> > >
> > > This series implements x2APIC mode in userspace local APIC and the
> > > RDMSR/WRMSR hel
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to su
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
> Hi everyone,
>
> This series implements x2APIC mode in userspace local APIC and the
> RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
> and AMD iommu are adjusted to support x2APIC interrupt remapping. With
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
series, we can now boot Linux kernel into x2APIC mode with TCG accel