On 2022/10/7 01:06, mchit...@ventanamicro.com wrote:
On Tue, 2022-10-04 at 21:23 +0800, weiwei wrote:
On 2022/10/4 14:51, mchit...@ventanamicro.com wrote:
On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote:
On 2022/10/3 19:47, Mayuresh Chitale wrote:
If smstateen is implemented and sstateen0.
On Tue, 2022-10-04 at 21:23 +0800, weiwei wrote:
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>
>
>
> On 2022/10/4 14:51,
> mchit...@ventanamicro.com wrote:
>
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> > On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote:
> >
> > > On 2022/10/3 19:47, Mayuresh Chitale wrote:
> > >
On 2022/10/4 14:51, mchit...@ventanamicro.com wrote:
On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote:
On 2022/10/3 19:47, Mayuresh Chitale wrote:
If smstateen is implemented and sstateen0.fcsr is clear then the
floating point
operations must return illegal instruction exception or virtual
inst
On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote:
> On 2022/10/3 19:47, Mayuresh Chitale wrote:
> > If smstateen is implemented and sstateen0.fcsr is clear then the
> > floating point
> > operations must return illegal instruction exception or virtual
> > instruction
> > trap, if relevant.
> >
> >
On 2022/10/3 19:47, Mayuresh Chitale wrote:
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23
target/riscv/insn_trans/
