Re: [PATCH v10 08/18] target/riscv: add rva22u64 profile definition

On Nov 3, 2023, at 21:46, Daniel Henrique Barboza wrote: > QEMU implements all possible extensions of this profile. All the so > called 'synthetic extensions' described in the profile that are cache > related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse, > Ziccamoa, Zicclsm) since

Re: [PATCH v10 08/18] target/riscv: add rva22u64 profile definition

On Nov 3, 2023, at 21:46, Daniel Henrique Barboza wrote: > > +/* > + * RVA22U64 defines some 'named features' or 'synthetic extensions' > + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa > + * and Zicclsm. We do not implement caching in QEMU so we'll consider > + * all these

Re: [PATCH v10 08/18] target/riscv: add rva22u64 profile definition

On 11/21/23 05:13, Jerry Shih wrote: On Nov 3, 2023, at 21:46, Daniel Henrique Barboza wrote: +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU

[PATCH v10 08/18] target/riscv: add rva22u64 profile definition

The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of fe