On Tue, Jul 5, 2022 at 1:20 AM Weiwei Li wrote:
>
>
> 在 2022/7/5 下午3:51, Atish Kumar Patra 写道:
> > On Mon, Jul 4, 2022 at 5:38 PM Weiwei Li wrote:
> >>
> >> 在 2022/7/4 下午11:26, Weiwei Li 写道:
> >>> 在 2022/6/21 上午7:15, Atish Patra 写道:
> The RISC-V privilege specification provides flexibility t
在 2022/7/5 下午3:51, Atish Kumar Patra 写道:
On Mon, Jul 4, 2022 at 5:38 PM Weiwei Li wrote:
在 2022/7/4 下午11:26, Weiwei Li 写道:
在 2022/6/21 上午7:15, Atish Patra 写道:
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However,
On Mon, Jul 4, 2022 at 5:38 PM Weiwei Li wrote:
>
>
> 在 2022/7/4 下午11:26, Weiwei Li 写道:
> >
> > 在 2022/6/21 上午7:15, Atish Patra 写道:
> >> The RISC-V privilege specification provides flexibility to implement
> >> any number of counters from 29 programmable counters. However, the QEMU
> >> implements
在 2022/7/4 下午11:26, Weiwei Li 写道:
在 2022/6/21 上午7:15, Atish Patra 写道:
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter wh
在 2022/6/21 上午7:15, Atish Patra 写道:
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many progr
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented b
