t;
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v1 3/8] aspeed/sdmc: Add AST2700 support
>
> Hi Jamin,
>
> On 29/2/24 08:23, Jamin Lin via wrote:
> > The SDRAM memory controller(DRAMC) controls the access to external
> > DDR4 and DDR5 SDRAM and power up
Hi Jamin,
On 29/2/24 08:23, Jamin Lin via wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max m
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
aspe
