Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates

2021-03-19 Thread Alistair Francis
On Wed, Mar 17, 2021 at 3:44 PM Richard Henderson wrote: > > On 3/17/21 11:39 AM, Alistair Francis wrote: > > @@ -1312,8 +1320,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, > > target_ulong *ret_value, > > return -RISCV_EXCP_ILLEGAL_INST; > > } > > ret = csr_ops[csrno]

Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates

2021-03-17 Thread Richard Henderson
On 3/17/21 11:39 AM, Alistair Francis wrote: @@ -1312,8 +1320,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, return -RISCV_EXCP_ILLEGAL_INST; } ret = csr_ops[csrno].predicate(env, csrno); -if (ret < 0) { -return ret; +if (ret >

[PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates

2021-03-17 Thread Alistair Francis
Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 80 +- 2 files changed, 46 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb2826a2..073a994d13 100644 --- a/target/riscv/c