Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT

2020-07-03 Thread Philippe Mathieu-Daudé
On 6/30/20 10:12 PM, Alistair Francis wrote: > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 > "memory: Revert "memory: accept mismatching sizes in > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit > accesses to the CLINT and QEMU would trigger a fault. Fix this failure >

Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT

2020-07-01 Thread Alistair Francis
On Tue, Jun 30, 2020 at 5:19 PM LIU Zhiwei wrote: > > > > On 2020/7/1 4:12, Alistair Francis wrote: > > Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 > > "memory: Revert "memory: accept mismatching sizes in > > memory_region_access_valid"" broke most RISC-V boards as they do 64 bit > > accesses

Re: [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT

2020-06-30 Thread LIU Zhiwei
On 2020/7/1 4:12, Alistair Francis wrote: Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 "memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"" broke most RISC-V boards as they do 64 bit accesses to the CLINT and QEMU would trigger a fault. Fix this failure by allow

[PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT

2020-06-30 Thread Alistair Francis
Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 "memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"" broke most RISC-V boards as they do 64 bit accesses to the CLINT and QEMU would trigger a fault. Fix this failure by allowing 8 byte accesses. Signed-off-by: Alistair F