On Tue, May 03, 2022 at 04:25:42PM +0100, frederic.kon...@xilinx.com wrote:
> From: Frederic Konrad
>
> The core and the vblend registers size are wrong, they should respectively be
> 0x3B0 and 0x1E0 according to:
>
> https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-regi
From: Frederic Konrad
The core and the vblend registers size are wrong, they should respectively be
0x3B0 and 0x1E0 according to:
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.
Let's fix that and use macros when creating the mmio region.
Fixes: 58ac48
