Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction

On Fri, Sep 3, 2021 at 7:23 AM Alistair Francis wrote: > > From: Alistair Francis > > The stval and mtval registers can optionally contain the faulting > instruction on an illegal instruction exception. This patch adds support > for setting the stval and mtval registers based on the CPU feature.

Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction

On 9/3/21 1:23 AM, Alistair Francis wrote: +target_ulong bins; Surely uint32_t, at least until 64-bit insn width is required. +TCGv tmp = temp_new(ctx); + +tcg_gen_movi_tl(tmp, ctx->opcode); +tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins)); tcg_gen_st_i32(tcg_c

[PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction

From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h|