Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-19 Thread Alistair Francis
On Wed, Mar 18, 2020 at 9:52 PM Palmer Dabbelt wrote: > > On Tue, 03 Mar 2020 17:16:59 PST (-0800), Alistair Francis wrote: > > The RISC-V spec specifies that when a write happens and the D bit is > > clear the implementation will set the bit in the PTE. It does not > > describe that the PTE being

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-18 Thread Palmer Dabbelt
On Tue, 03 Mar 2020 17:16:59 PST (-0800), Alistair Francis wrote: The RISC-V spec specifies that when a write happens and the D bit is clear the implementation will set the bit in the PTE. It does not describe that the PTE being dirty means that we should provide write access. This patch removes

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-13 Thread Alistair Francis
On Thu, Mar 12, 2020 at 10:26 PM Richard Henderson wrote: > > On 3/12/20 3:10 PM, Alistair Francis wrote: > >> I still think this must be a guest (or nested guest) bug related to > >> clearing > >> PTE bits and failing to flush the TLB properly. > > > > It think so as well now. I have changed the

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-12 Thread Richard Henderson
On 3/12/20 3:10 PM, Alistair Francis wrote: >> I still think this must be a guest (or nested guest) bug related to clearing >> PTE bits and failing to flush the TLB properly. > > It think so as well now. I have changed the Linux guest and Hypervisor > to be very aggressive with flushing but still

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-12 Thread Alistair Francis
On Wed, Mar 4, 2020 at 9:34 AM Richard Henderson wrote: > > On 3/3/20 5:16 PM, Alistair Francis wrote: > > The RISC-V spec specifies that when a write happens and the D bit is > > clear the implementation will set the bit in the PTE. It does not > > describe that the PTE being dirty means that we

Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-04 Thread Richard Henderson
On 3/3/20 5:16 PM, Alistair Francis wrote: > The RISC-V spec specifies that when a write happens and the D bit is > clear the implementation will set the bit in the PTE. It does not > describe that the PTE being dirty means that we should provide write > access. This patch removes the write access

[PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs

2020-03-03 Thread Alistair Francis
The RISC-V spec specifies that when a write happens and the D bit is clear the implementation will set the bit in the PTE. It does not describe that the PTE being dirty means that we should provide write access. This patch removes the write access granted to pages when the dirty bit is set. Follow