On 02.10.19 09:04, David Hildenbrand wrote:
> On 01.10.19 23:59, Richard Henderson wrote:
>> On 10/1/19 12:47 PM, David Hildenbrand wrote:
>>> On 01.10.19 21:17, Richard Henderson wrote:
On 10/1/19 11:16 AM, David Hildenbrand wrote:
> +static inline bool should_interrupt_instruction(CPUSta
On 01.10.19 23:59, Richard Henderson wrote:
> On 10/1/19 12:47 PM, David Hildenbrand wrote:
>> On 01.10.19 21:17, Richard Henderson wrote:
>>> On 10/1/19 11:16 AM, David Hildenbrand wrote:
+static inline bool should_interrupt_instruction(CPUState *cs)
+{
+/*
+ * Somethin
On 10/1/19 12:47 PM, David Hildenbrand wrote:
> On 01.10.19 21:17, Richard Henderson wrote:
>> On 10/1/19 11:16 AM, David Hildenbrand wrote:
>>> +static inline bool should_interrupt_instruction(CPUState *cs)
>>> +{
>>> +/*
>>> + * Something asked us to stop executing chained TBs, e.g.,
>>>
On 01.10.19 21:17, Richard Henderson wrote:
> On 10/1/19 11:16 AM, David Hildenbrand wrote:
>> +static inline bool should_interrupt_instruction(CPUState *cs)
>> +{
>> +/*
>> + * Something asked us to stop executing chained TBs, e.g.,
>> + * cpu_interrupt() or cpu_exit().
>> + */
>>
On 10/1/19 11:16 AM, David Hildenbrand wrote:
> +static inline bool should_interrupt_instruction(CPUState *cs)
> +{
> +/*
> + * Something asked us to stop executing chained TBs, e.g.,
> + * cpu_interrupt() or cpu_exit().
> + */
> +if ((int32_t)atomic_read(&cpu_neg(cs)->icount_de
MVCL is interruptible and we should check for interrupts and process
them after writing back the variables to the registers.
I can see both checks triggering. Most of them pass the first check,
however, sometimes also the second check strikes and an interrupt gets
delivered. (I assume pending inte
