@nvidia.com; joao.m.mart...@oracle.com; Tian,
>> Kevin ; Liu, Yi L ; Peng, Chao P
>> ; Paolo Bonzini ; Richard
>> Henderson ; Eduardo Habkost
>> ; Marcel Apfelbaum
>> Subject: Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in
>> scalable modren mode
&
sow...@redhat.com;
>j...@nvidia.com; nicol...@nvidia.com; joao.m.mart...@oracle.com; Tian,
>Kevin ; Liu, Yi L ; Peng, Chao P
>; Paolo Bonzini ; Richard
>Henderson ; Eduardo Habkost
>; Marcel Apfelbaum
>Subject: Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in
>scalable mo
Hi Zhenzhong
On 22/05/2024 08:23, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
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>
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39
