Re: [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

在 2022/3/17 下午3:26, ~eopxd 写道: From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elem

[PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m