Re: [PATCH qemu] target/riscv: Check ext_zca for misaligned return address of mret/sret.

On Thu, Jan 16, 2025 at 1:32 PM ~yuming wrote: > > From: Yu-Ming Chang > > Only check misa.C will cause issues when ext_zca is enabled without > misa.C being set. For example, only enable ext_zce. Thanks for the patch! I'm not clear what the problem is and what this commit fixes. Do you mind up

[PATCH qemu] target/riscv: Check ext_zca for misaligned return address of mret/sret.

From: Yu-Ming Chang Only check misa.C will cause issues when ext_zca is enabled without misa.C being set. For example, only enable ext_zce. Signed-off-by: Yu-Ming Chang --- target/riscv/op_helper.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/op