Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2022-01-05 Thread Thomas Huth
On 16/12/2021 14.16, Nico Boehr wrote: Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, as per the principles of operation, bit 5 is ignored in MSCH and bits 0, 1, 6 and 7 need to be zero. As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used by ioinst_ha

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-23 Thread Cornelia Huck
On Thu, Dec 23 2021, Halil Pasic wrote: > On Wed, 22 Dec 2021 17:46:11 +0100 > Cornelia Huck wrote: > >> On Thu, Dec 16 2021, Nico Boehr wrote: >> >> > Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, >> > as per the principles of operation, bit 5 is ignored in MSCH and

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-23 Thread Halil Pasic
On Wed, 22 Dec 2021 17:46:11 +0100 Cornelia Huck wrote: > On Thu, Dec 16 2021, Nico Boehr wrote: > > > Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > > as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > > 1, 6 and 7 need to be zero. > > > > As

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-22 Thread Cornelia Huck
On Thu, Dec 16 2021, Nico Boehr wrote: > Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > 1, 6 and 7 need to be zero. > > As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used > b

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-20 Thread Halil Pasic
On Mon, 20 Dec 2021 11:44:44 +0100 Pierre Morel wrote: > > > > The PoP says that the machine shall ignore other fields > > of the PMCW when an MSCH is performed. I.e. we should not update > > "our" pmcw.flags bit 5 from 0 to 1 even if 1 was supplied, and > > thus STSCH should keep storing the bi

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-20 Thread Pierre Morel
On 12/17/21 20:28, Halil Pasic wrote: On Fri, 17 Dec 2021 18:13:47 +0100 Pierre Morel wrote: Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, as per the principles of operation, bit 5 is ignored in MSCH and bits 0, 1, 6 and 7 need to be zero. On a second thought, d

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-17 Thread Halil Pasic
On Fri, 17 Dec 2021 18:13:47 +0100 Pierre Morel wrote: > >> Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > >> as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > >> 1, 6 and 7 need to be zero. > > > > On a second thought, don't we have to make

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-17 Thread Pierre Morel
On 12/17/21 14:58, Halil Pasic wrote: On Thu, 16 Dec 2021 14:16:57 +0100 Nico Boehr wrote: Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, as per the principles of operation, bit 5 is ignored in MSCH and bits 0, 1, 6 and 7 need to be zero. On a second thought, don

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-17 Thread Halil Pasic
On Fri, 17 Dec 2021 14:58:11 +0100 Halil Pasic wrote: > On Thu, 16 Dec 2021 14:16:57 +0100 > Nico Boehr wrote: > > > Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > > as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > > 1, 6 and 7 need to be ze

Re: [PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-17 Thread Halil Pasic
On Thu, 16 Dec 2021 14:16:57 +0100 Nico Boehr wrote: > Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > 1, 6 and 7 need to be zero. On a second thought, don't we have to make sure then that bit 5

[PATCH qemu] s390x/css: fix PMCW invalid mask

2021-12-16 Thread Nico Boehr
Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, as per the principles of operation, bit 5 is ignored in MSCH and bits 0, 1, 6 and 7 need to be zero. As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used by ioinst_handle_msch(), adjust the mask accordingly.