Re: [PATCH V3 5/6] target/riscv: Add V extension state description

On Fri, Oct 23, 2020 at 2:18 AM Yifei Jiang wrote: > > In the case of supporting V extension, add V extension description > to vmstate_riscv_cpu. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > targe

[PATCH V3 5/6] target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Richard Henderson --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/ma