Re: [PATCH RFC] target/arm: Implement SVE2 gather load insns

2020-04-24 Thread Richard Henderson
On 4/22/20 8:23 AM, Stephen Long wrote: > Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load > insns. > > 64-bit > * LDNT1SB > * LDNT1B (vector plus scalar) > * LDNT1SH > * LDNT1H (vector plus scalar) > * LDNT1SW > * LDNT1W (vector plus scalar) > * LDNT1D (vector plus scalar) > >

[PATCH RFC] target/arm: Implement SVE2 gather load insns

2020-04-22 Thread Stephen Long
Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H