On Wed, Feb 15, 2023 at 08:17:22PM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 20:17:22 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 14/18] i386: Add cache topology info in
> CPUCacheInfo
>
> Hi Zhao,
>
> 在 2023/2/13 17:3
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
ca
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a sp
