On Fri, 1 Mar 2024 at 21:54, Richard Henderson
wrote:
>
> On 3/1/24 08:32, Peter Maydell wrote:
> > +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
> > +{
> > +if ((env->cp15.scr_el3 & SCR_ECVEN) &&
> > +FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
> > +arm_is_e
On 3/1/24 08:32, Peter Maydell wrote:
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
+{
+if ((env->cp15.scr_el3 & SCR_ECVEN) &&
+FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
+arm_is_el2_enabled(env) &&
+(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
implemented. This is similar to the existing CNTVOFF_EL2, except
that it controls a hypervisor-adjustable offset made to the physical
counter and timer.
Implement the handling for this register, which includes control/trap
bits in
