On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li wrote:
>
> - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 25 ++---
> 1 file changed,
- add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9bda1ff993..0d8