Re: [PATCH 4/5] target/ppc: books: External interrupt cleanup

2022-01-25 Thread Cédric Le Goater
On 1/24/22 19:46, Fabiano Rosas wrote: Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_H

[PATCH 4/5] target/ppc: books: External interrupt cleanup

2022-01-24 Thread Fabiano Rosas
Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_HV in msr_mask. Signed-off-by: Fabiano Ro