On 23/12/2023 11:47, Paolo Bonzini wrote:
The linear address is the one that has the segment base added, and it is
not truncated to 16 bits (otherwise the whole A20 thing would not
exist). The same should be true of e.g. an FSAVE instruction; it would
allow access slightly beyond the usual 1M+6
Il sab 23 dic 2023, 11:34 Michael Brown ha scritto:
> I am confused by how BOUND can result in an access to a linear address
> outside of the address-size range. I don't know the internals well
> enough, but I'm guessing it might be in the line in helper_boundl():
>
> high = cpu_ldl_data_ra
On 22/12/2023 17:59, Paolo Bonzini wrote:
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit o
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory a
