Re: [PATCH 20/28] target/arm: Improve REV32

2021-06-21 Thread Peter Maydell
On Mon, 14 Jun 2021 at 09:38, Richard Henderson wrote: > > For the sf version, we are performing two 32-bit bswaps > in either half of the register. This is equivalent to > performing one 64-bit bswap followed by a rotate. > > For the non-sf version, we can remove TCG_BSWAP_IZ > and the preceding

Re: [PATCH 20/28] target/arm: Improve REV32

2021-06-14 Thread Philippe Mathieu-Daudé
On 6/14/21 10:37 AM, Richard Henderson wrote: > For the sf version, we are performing two 32-bit bswaps > in either half of the register. This is equivalent to > performing one 64-bit bswap followed by a rotate. > > For the non-sf version, we can remove TCG_BSWAP_IZ > and the preceding zero-exten

[PATCH 20/28] target/arm: Improve REV32

2021-06-14 Thread Richard Henderson
For the sf version, we are performing two 32-bit bswaps in either half of the register. This is equivalent to performing one 64-bit bswap followed by a rotate. For the non-sf version, we can remove TCG_BSWAP_IZ and the preceding zero-extension. Cc: Peter Maydell Signed-off-by: Richard Henderson