subject:"\[PATCH 2\/2\] targett\/riscv\: rva\: Correctly generate a store\/amo fault"

Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault

2022-01-26 Thread Weiwei Li

It seems that target is miswritten to "targett" in commit message. Regards, Weiwei Li 在 2022/1/24 上午8:59, Alistair Francis 写道: From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for the

Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault

2022-01-23 Thread LIU Zhiwei

On 2022/1/24 上午8:59, Alistair Francis wrote: From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for the guest. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: A

[PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault

2022-01-23 Thread Alistair Francis

From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for the guest. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Alistair Francis --- target/riscv/insn_trans/tra